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| H Hermetically Sealed, Transistor Output Optocouplers for Analog and Digital Applications Technical Data 4N55* 5962-87679 HCPL-553X HCPL-653X HCPL-655X 5962-90854 HCPL-550X *See matrix for available extensions. Features * Dual Marked with Device Part Number and DESC Drawing Number * Manufactured and Tested on a MIL-PRF-38534 Certified Line * QML-38534, Class H and K * Five Hermetically Sealed Package Configurations * Performance Guaranteed, Over -55C to +125C * High Speed: Typically 400 kBit/s * 9 MHz Bandwidth * Open Collector Output * 2-18 Volt VCC Range * 1500 Vdc Withstand Test Voltage * High Radiation Immunity * 6N135, 6N136, HCPL-2530/ -2531, Function Compatibility * Reliability Data * Analog Signal Ground Isolation (see Figures 7, 8, and 13) * Isolated Input Line Receiver * Isolated Output Line Driver * Logic Ground Isolation * Harsh Industrial Environments * Isolation for Test Equipment Systems improve the speed up to a hundred times that of a conventional phototransistor optocoupler by reducing the base-collector capacitance. These devices are suitable for wide bandwidth analog applications, as well as for interfacing TTL to LSTTL or CMOS. Current Transfer Ratio (CTR) is 9% minimum at IF = 16 mA. The 18 V VCC Description These units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appropriate DESC Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DESC Qualified Manufacturers List QML-38534 for Hybrid Microcircuits. Each channel contains a GaAsP light emitting diode which is optically coupled to an integrated photon detector. Separate connections for the photodiodes and output transistor collectors Truth Table (Positive Logic) Input On (H) Off (L) Output L H Functional Diagram Multiple Channel Devices Available VCC VB VO Applications * Military and Space * High Reliability Systems * Vehicle Command, Control, Life Critical Systems * Line Receivers * Switching Power Supply * Voltage Level Shifting GND CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 5965-3002E 1-559 capability will enable the designer to interface any TTL family to CMOS. The availability of the base lead allows optimized gain/ bandwidth adjustment in analog applications. The shallow depth of the IC photodiode provides better radiation immunity than conventional phototransistor couplers. These products are also available with the transistor base node connected to improve common mode noise immunity and ESD susceptibility. In addition, higher CTR minimums are available by special request. Package styles for these parts are 8 and 16 pin DIP through hole (case outlines P and E respectively), 16 pin DIP flat pack (case outline F), and leadless ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating options, see Selection Guide Table for details. Standard Military Drawing (SMD) parts are available for each package and lead style. Because the same functional die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to package variations and limitations and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other part's performance for die related reliability and certain limited radiation test results. 8 Pin Ceramic DIP Single Channel Schematic ANODE 2 + IF ICC 8 IB IO 7 6 VCC VB VO VF CATHODE - 3 5 GND Note base pin 7. Selection Guide-Package Styles and Lead Configuration Options Package Lead Style Channels Common Channel Wiring HP Part # & Options Commercial MIL-PRF-38534, Class H MIL-PRF-38534, Class K Standard Lead Finish Solder Dipped Butt Cut/Gold Plate Gull Wing/Soldered SMD Part # Prescript for all below Either Gold or Solder Gold Plate Solder Dipped Butt Cut/Gold Plate Butt Cut/Soldered Gull Wing/Soldered *JEDEC registered part. 16 Pin DIP Through Hole 2 None 4N55* 4N55/883B HCPL-257K Gold Plate Option #200 Option #100 Option #300 59628767901EX 8767901EC 8767901EA 8767901UC 8767901UA 8767901TA 8 Pin DIP Through Hole 1 None HCPL-5500 HCPL-5501 HCPL-550K Gold Plate Option #200 Option #100 Option #300 59629085401HPX 9085401HPC 9085401HPA 9085401HYC 9085401HYA 9085401HXA 8 Pin DIP Through Hole 2 VCC GND HCPL-5530 HCPL-5531 HCPL-553K Gold Plate Option #200 Option #100 Option #300 59628767902PX 8767902PC 8767902PA 8767902YC 8767902YA 8767902XA 16 Pin Flat Pack Unformed Leads 4 VCC GND HCPL-6550 HCPL-6551 HCPL-655K Gold Plate 20 Pad LCCC Surface Mount 2 None HCPL-6530 HCPL-6531 HCPL-653K Solder Pads 59628767904FX 8767904FC 596287679032X 87679032A 1-560 Functional Diagrams 16 Pin DIP Through Hole 2 Channels 1 VB1 VOC1 VO1 GND 16 1 VCC VB VOUT 8 1 VCC VO1 VO2 8 2 VCC VO1 VO2 VO3 VO4 GND 15 14 8 Pin DIP Through Hole 1 Channel 8 Pin DIP Through Hole 2 Channels 16 Pin Flat Pack Unformed Leads 4 Channels 1 16 20 Pad LCCC Surface Mount 2 Channels 15 14 VCC2 19 20 VB2 VO2 GND2 VO1 GND1 VCC1 13 12 2 3 4 15 2 7 6 5 2 3 4 7 14 3 6 3 4 2 13 10 13 4 GND GND 5 3 VB1 9 7 8 5 VB2 VCC2 GND VO2 12 5 12 6 7 8 11 10 9 6 7 8 11 10 9 Note: 8 pin DIP and flat pack devices have common VCC and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages have isolated channels with separate VCC and ground connections. Outline Drawings 16 Pin DIP Through Hole, 2 Channels 20.06 (0.790) 20.83 (0.820) 0.89 (0.035) 1.65 (0.065) 4.45 (0.175) MAX. 8.13 (0.320) MAX. 0.51 (0.020) MIN. 3.81 (0.150) MIN. 0.20 (0.008) 0.33 (0.013) 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MAX. 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Leaded Device Marking HP LOGO HP P/N DESC SMD* DESC SMD* PIN ONE/ ESD IDENT HP QYYWWZ XXXXXX XXXXXXX XXX USA * 50434 * QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. HP FSCN* Leadless Device Marking HP LOGO HP P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. HP QYYWWZ XXXXXX * XXXX XXXXXX USA 50434 *QUALIFIED PARTS ONLY *QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) DESC SMD* DESC SMD* HP FSCN* 1-561 Outline Drawings (contd.) 16 Pin Flat Pack, 4 Channels 7.24 (0.285) 6.99 (0.275) 2.29 (0.090) MAX. 1.27 (0.050) REF. 11.13 (0.438) 10.72 (0.422) 0.46 (0.018) 0.36 (0.014) 8.13 (0.320) MAX. 2.85 (0.112) MAX. 0.88 (0.0345) MIN. 0.89 (0.035) 0.69 (0.027) 5.23 (0.206) MAX. 9.02 (0.355) 8.76 (0.345) 0.31 (0.012) 0.23 (0.009) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 20 Terminal LCCC Surface Mount, 2 Channels 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 PLCS) 1.14 (0.045) 1.40 (0.055) 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 0.64 (0.025) (20 PLCS) 1.52 (0.060) 2.03 (0.080) 8 Pin DIP Through Hole, 1 and 2 Channel 9.40 (0.370) 9.91 (0.390) 0.76 (0.030) 1.27 (0.050) 4.32 (0.170) MAX. 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298) TERMINAL 1 IDENTIFIER 2.16 (0.085) METALIZED CASTILLATIONS (20 PLCS) 0.51 (0.020) 0.51 (0.020) MIN. 3.81 (0.150) MIN. 0.20 (0.008) 0.33 (0.013) 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX. 1-562 Hermetic Optocoupler Options Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) 200 300 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and 16 pin DIP. DESC drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped leads. 5.57 (0.180) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 5.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) 5.57 (0.180) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 5 MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 1-563 Absolute Maximum Ratings (No derating required up to +125C) Storage Temperature Range, TS ................................... -65C to +150C Operating Temperature, TA .......................................... -55C to +125C Case Temperature, TC ................................................................ +170C Junction Temperature, TJ ........................................................... +175C Lead Solder Temperature ............................................... 260C for 10 s Peak Forward Input Current, (each channel, 1 ms duration), IF PK .............................................................. 40 mA Average Input Forward Current, IF AVG (each channel) ................ 20 mA Reverse Input Voltage, BVR ...................... See Electrical Characteristics Average Output Current, IO (each channel) ................................... 8 mA Peak Output Current, IO (each channel) ...................................... 16 mA Supply Voltage, VCC ......................................................... -0.5 V to 20 V Output Voltage, VO (each channel) ................................... -0.5 V to 20 V Input Power Dissipation (each channel) ..................................... 36 mW Output Power Dissipation (each channel) .................................. 50 mW Package Power Dissipation, PD (each channel) ........................ 200 mW Single Channel 8 Pin, Dual Channel 16 Pin, and LCCC Only Emitter Base Reverse Voltage, VEBO ............................................... 3.0 V Base Current, IB (each channel) .................................................... 5 mA ESD Classification (MIL-STD-883, Method 3015) 4N55, 4N55/883B, HCPL-5500/01, and HCPL-6530/31 ..................................................................... (), Class 1 HCPL-5530/31, HCPL-6550/51 ....................................... (Dot), Class 3 Recommended Operating Conditions Parameter Input Current, Low Level Input Current, High Level Supply Voltage, Output Symbol IFL IFH VCC Min. 12 2 Max. 250 20 18 Units A mA V 1-564 Electrical Characteristics (TA = -55C to +125C, unless otherwise specified) Parameter Current Transfer Ration Logic High Output Current Output Leakage Current Input-Output Insulation Leakage Current Input Forward Voltage Reverse Breakdown Voltage Single Channel Dual Channel Quad Channel Logic Single Low Channel Supply Dual Current Channel Quad Channel Propagation Delay Time to Logic High at Output Propagation Delay Time to Logic Low at Output Logic High Supply Current Limits Group A[12] Symbol Test Conditions Sub-groups Min. Typ.** Max. Units Fig. CTR* VO = 0.4 V, IF = 16 mA, 1, 2, 3 9 20 % 2, 3 VCC = 4.5 V IOH IF = 0, 1, 2, 3 5 100 A 4 IF (other channels) = 20 mA, VO = VCC = 18 V IOLeak* IF = 250 A, 1, 2, 3 30 250 A 4 IF (other channels) = 20 mA, VO = VCC = 18 V II-O* VI-O = 1500 Vdc, 1 1.0 A RH = 45% TA = 25C, t = 5 s VF* IF = 20 mA 1, 2, 3 1.55 1.8 V 1 1.9 BVR* IR = 10 A 1, 2, 3 5 V 3 ICCH* VCC = 18 V, IF = 0 mA 1, 2, 3 0.1 10 A VCC = 18 V, IF = 0 mA (all channels) VCC = 18 V, IF = 0 mA (all channels) VCC = 18 V, IF = 20 mA VCC = 18 V, IF1 = IF2 = 20 mA VCC = 18 V, IF1 = IF2 = IF3 = IF4 = 20 mA RL = 8.2 k, CL = 50 pF, IF = 16 mA, VCC = 5 V 0.2 0.4 1, 2, 3 35 70 140 9, 10, 11 1.0 20 40 200 400 800 6.0 s A 5 Note 1, 2, 10 1 1 3, 9 1, 14 1, 13 1, 14 1, 13 1 1, 4 1 1 1, 4 1 ICCL* tPLH* 6, 9 1, 6 tPHL* 0.4 2.0 *For JEDEC registered parts. **All typical values are at VCC = 5 V, TA = 25C. 1-565 Typical Characteristics, TA = 25C, VCC = 5 V Parameter Input Capacitance Input Diode Temperature Coefficient Resistance (Input-Output) Capacitance (Input-Output) Transistor DC Current Gain Small Signal Current Transfer Ratio Common Mode Transient Immunity at Logic High Level Output Common Mode Transient Immunity at Logic Low Level Output Bandwidth Multi-Channel Product Only Input-Input Insulation Leakage Current Resistance (Input-Input) Capacitance (Input-Input) Symbol CIN VF TA RI-O CI-O hFE IO IF |CMH| Typ. 60 -1.5 1012 1.0 250 21 1000 Units pF mV/C pF % V/s Test Conditions VF = 0 V, f = 1 MHz IF = 20 mA VI-O 500 V f = 1 MHz VO = 5 V, IO = 3 mA VCC = 5 V, VO = 2 V IF = 0 mA, RL = 8.2 k, VO (min) = 2.0 V VCM = 10 VP-P IF = 16 mA, RL = 8.2 k, VO (max) = 0.8 V VCM = 10 VP-P Fig. Note 1 1 3 1, 11 1 1 1, 7 7 10 |CML| -1000 V/s 10 1, 7 BW 9 MHz 8 8 II-I RI-I CI-I 1 1012 0.8 pA pF Relative Humidity = 45% VI-I = 500 V, t = 5 s VI-I = 500 V f = 1 MHz 5, 9 5 5 Notes: 1. Each channel of a multi-channel device. 2. Current Transfer Ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100%. CTR is known to degrade slightly over the unit's lifetime as a function of input current, temperature, signal duty cycle, and system on time. Refer to Application Note 1002 for more detail. ln short, it is recommended that designers allow at least 20-25% guardband for CTR degradation. 3. All devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 4. The 4N55, 4N55/883B, HCPL-6530 and HCPL-6531 dual channel parts function as two independent single channel units. Use the single channel parameter limits. IF = 0 mA for channel under test and IF = 20 mA for other channels. 5. Measured between adjacent input pairs shorted together for each multichannel device. 6. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse. 7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V). 8. Bandwidth is the frequency at which the ac output voltage is 3 dB below the low frequency asymptote. For the HCPL-5530 the typical bandwidth is 2 MHz. 9. This is a momentary withstand test, not an operating condition. 10. Higher CTR minimums are available to support special applications. 11. Measured between each input pair shorted together and all output connections for that channel shorted together. 12. Standard parts receive 100% testing at 25C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 13. Not required for 4N55, 4N55/883B and 5962-8767901 types. 14. Required for 4N55, 4N55/883B and 5962-8767901 types only. 1-566 Figure 1. Input Diode Forward Current vs. Forward Voltage. Figure 2. DC and Pulsed Transfer Characteristic. Figure 3. Normalized Current Transfer Ratio vs. Input Diode Forward Current. IOH - LOGIC HIGH OUTPUT CURRENT - A 100 IF = 250 A, IF (OTHER CHANNELS) = 20 mA 10 IF = 0 A, IF (OTHER CHANNELS) = 20 mA IF = IF (OTHER CHANNELS) = 0 mA 1 0.1 0.01 VCC = VO = 18 V 0.001 -60 -40 -20 0 20 40 60 80 100 120 140 TA - TEMPERATURE - C Figure 4. Logic High Output Current vs. Temperature. Figure 5. Logic Low Supply Current vs. Input Diode Forward Current. Figure 6. Propagation Delay vs. Temperature. Figure 7. Normalized Small Signal Current Transfer Ratio vs. Quiescent Input Current. 1-567 +12 V 0.1 F VIN 51 1 k 0.1 F 2.1 k 47 F Q1 100 RF D.U.T. VCC VO VB 15 k GND 22 1N4150 +12 V 1.2 k 9.1 k Q2 100 470 Q3 0.01 F 0.01 F VO (1 M, 12 pF TEST INPUT) SINGLE CHANNEL TESTING, INDEPENDENT VCC DEVICES TRIM FOR UNITY GAIN Q1, Q2, Q3: 2N3904 TYPICAL LINEARITY = +3 % AT VIN = 1 VP-P TYPICAL SNR = 50 dB TYPICAL RF = 375 TYPICAL VO dc = 3.8 V TYPICAL IF = 9 mA NORMALIZED RESPONSE - dB +15 +10 +5 0 -5 -10 -15 -20 0.1 1.0 10 100 COMMON VCC DEVICES TA = 25 C INDEPENDENT VCC DEVICES +5 V SET IF AC INPUT 0.1 F 560 100 20 k 2N3053 1.6 Vdc 0.25 VP-P ac D.U.T. VCC 100 +15 V VO GND COMMON VCC DEVICES f - FREQUENCY - MHz Figure 8. Frequency Response. PULSE GEN. ZO = 50 tr = 5 ns IF D.U.T. VCC RL +5 V IF MONITOR 100 GND VO CL* = 50 pF SINGLE CHANNEL OR COMMON VCC DEVICES 10 % DUTY CYCLE 1/f < 100 s NOTES: * CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE. BASE LEAD NOT CONNECTED. Figure 9. Switching Test Circuit.* *JEDEC Registered Data. 1-568 IF B RM D.U.T. VCC A RL VO +5 V VFF GND SINGLE CHANNEL OR COMMON VCC DEVICES VCM + - PULSE GEN. NOTE: BASE LEAD NOT CONNECTED. Figure 10. Test Circuit for Transient Immunity and Typical Waveforms. 5V VCC 220 D.U.T. VCC TTL LOGIC GATE 0.01 F GND EACH CHANNEL RL Logic Family Device No. VCC RL 5% Tolerance LSTTL 54LS14 5V 18 k* CMOS CD40106BM 5V 15 V 8.2 k 22 k *The equivalent output load resistance is affected by the LSTTL input current and is approximately 8.2 k. This is a worst case design which takes into account 25% degradation of CTR. See App. Note 1002 to assess actual degradation and lifetime. Figure 11. Recommended Logic Interface. VCC D.U.T.* VCC (EACH INPUT) + VIN - VO GND (EACH OUTPUT) 0.1 F VOC NOMINAL CONDITIONS PER CHANNEL: IF = 20 mA IO = 4 mA ICC = 30 A NOTE: BASE LEAD NOT CONNECTED. TA = +125 C Figure 12. Operating Circuit for Burn-In and Steady State Life Tests. All Channels Tested Simultaneously. 1-569 HCPL-5530 - U1 + IF1 1 8 IC 2 V IN I F2 3 - U2 + R1 2.7 k U1 , U2 , U3 , U4 , LM307 IC = K1 1 2 220 - U3 + 2 IC 2 R3 OFFSET ADJUST 5 k + 1 7 6 R4 1 k 5 k GAIN ADJUST 50 k VOUT - 4 5 -15 V - U4 + 2 R2 2.7 k R5 IF IF n1 6 mA I CC 1 1 2 IC = K2 2 IF IF n2 -15 V 2 Figure 13. Isolation Amplifier Application Circuit. Description The schematic uses a dualchannel, high-speed optocoupler (HCPL-5530) to function as a servo type dc isolation amplifier. This circuit operates on the principle that two optocouplers will track each other if their gain changes by the same amount over a specific operating region. Performance of Circuit * 1% linearity for 10 V peak-topeak dynamic range * Gain drift: -0.03%/C * Offset Drift: 1 mV/C * 25 kHz bandwidth (limited by Op-Amps U1, U2) MIL-PRF-38534 Class H, Class K, and DESC SMD Test Program Hewlett-Packard's Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Classes H and K. Class H devices are also in compliance with DESC drawings 5962-87679, and 5962-90854. Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534. 1-570 |
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